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          <h3 id="一、功能介绍"><a href="#一、功能介绍" class="headerlink" title="一、功能介绍"></a>一、功能介绍</h3><p>​        调用时钟锁相环IP通过输入的50M时钟产生100M甚至更高的时钟源，在学习7系列的时钟锁相环IP的使用的同时，学会如何在VIVADO下使调用IP核。实现效果：锁相环时钟输出，最后驱动流水灯模块。</p>
<h3 id="二、时钟模块IP调用"><a href="#二、时钟模块IP调用" class="headerlink" title="二、时钟模块IP调用"></a>二、时钟模块IP调用</h3><p>​        工程管理栏点击 Add Sources 添加新建文件：pll_clock_top.v，模块名pll_clock_top，添加新建完成之后点击工程管理栏的PROJECT MANAGER下的IP Catalog。我们在IP Catalog输入clock，下拉界面找到clocking wizard并且双击，打开IP配置界面：</p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261521257.png"></p>
<p>​        修改配置与下图保持一致：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261619566.png" style="zoom:80%;">

<p>​        输出时钟配置如下，只输出一路时钟，100M频率：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261620797.png" style="zoom:80%;">

<p>​        右边下拉界面，最下面设置reset信号为低有效，最后点击OK完成配置：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261620454.png" style="zoom:80%;">

<p>弹出对话框，点击OK。</p>
<p>最后，生成输出文件对话框，我们点击Generate。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261621075.png" style="zoom:67%;">

<p>​        我们回到Sources界面，可以看到，Design Sources出现了clk_wiz_0的IP核添加进来了。点<br>击左边IP核的箭头，打开IP的架构。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261622557.png" style="zoom:80%;">

<p>弹出的对话框点击OK：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261622797.png" style="zoom:67%;">

<p>​        Sources下的Design Sources的IP核下出现了一个时钟模块的顶层.v文件。我们双击打开他，</p>
<p>可以看到模块的名称和接口信号。我们将这个时钟模块例化到pll_clock_top.v里面。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261623166.png" style="zoom:67%;">

<p>​        最后，在整个pll_top_top.v文件中添加如下代码：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261625389.png" style="zoom:80%;">

<p>​        最后，综合布局布线生成比特文件，我们下载到板子上，可以看到，闪灯比我们之前的实验效果要快一倍。因为我们时钟倍频100M速度，而之前闪灯的时钟直接使用外部晶振，速度是50M。</p>

      
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          <p>​        原文地址：<a target="_blank" rel="noopener" href="https://blog.csdn.net/Arvin_ing/article/details/127093691">https://blog.csdn.net/Arvin_ing/article/details/127093691</a></p>
<h3 id="1-什么是模块例化？为什么要例化？"><a href="#1-什么是模块例化？为什么要例化？" class="headerlink" title="1.什么是模块例化？为什么要例化？"></a>1.什么是模块例化？为什么要例化？</h3><p>​        模块例化可以理解成模块调用。对于一个FPGA工程，通常是由一个顶层模块与多个功能子模块组成，为了实现顶层模块与子模块的连接，需要进行模块间的例化（或说是调用）。在一个FPGA项目工程中，其输入、输出端口命名通常在设计前期就已确定下来，但会存在一些中间变量，一个工程可能会让不同的工程师在不同的时间段内共同完成，不同的人对于这些变量的命名会有所不同，故例化很有必要。<br>​        注：一个顶层模块可在其内部例化多个相同的模块。</p>
<h3 id="2-实例说明例化方法"><a href="#2-实例说明例化方法" class="headerlink" title="2.实例说明例化方法"></a>2.实例说明例化方法</h3><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//计时模块（仅显示端口及参数）</span></span><br><span class="line"><span class="keyword">module</span> time_count(</span><br><span class="line">	<span class="keyword">input</span>		clk ,                       <span class="comment">// 时钟信号</span></span><br><span class="line">	<span class="keyword">input</span>		rst_n ,                     <span class="comment">// 复位信号</span></span><br><span class="line"> </span><br><span class="line">	<span class="keyword">output</span> <span class="keyword">reg</span>  flag                        <span class="comment">// 一个时钟周期的脉冲信号</span></span><br><span class="line">);</span><br><span class="line"> </span><br><span class="line"><span class="comment">//parameter define</span></span><br><span class="line">	<span class="keyword">parameter</span> MAX_NUM = <span class="number">25000_000</span>;         <span class="comment">// 计数器最大计数值</span></span><br><span class="line">......(省略功能代码)</span><br><span class="line"> </span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//数码管静态显示模块（仅显示端口及参数）</span></span><br><span class="line"><span class="keyword">module</span> seg_led_static ( </span><br><span class="line">	<span class="keyword">input</span> 			 clk ,                <span class="comment">// 时钟信号</span></span><br><span class="line">	<span class="keyword">input</span> 			 rst_n ,              <span class="comment">// 复位信号（低有效）</span></span><br><span class="line">	<span class="keyword">input</span> 			 add_flag,            <span class="comment">// 数码管变化的通知信号</span></span><br><span class="line">	</span><br><span class="line">	<span class="keyword">output</span> <span class="keyword">reg</span> [<span class="number">5</span>:<span class="number">0</span>] sel ,                <span class="comment">// 数码管位选</span></span><br><span class="line">	<span class="keyword">output</span> <span class="keyword">reg</span> [<span class="number">7</span>:<span class="number">0</span>] seg_led              <span class="comment">// 数码管段选</span></span><br><span class="line"> );</span><br><span class="line">......（省略功能代码）</span><br><span class="line"> </span><br><span class="line"> <span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//顶层模块（着重看下面“例化计时模块”、“例化数码管静态显示模块”）</span></span><br><span class="line"><span class="keyword">module</span> seg_led_static_top (</span><br><span class="line">	<span class="keyword">input</span> 		 sys_clk ,              <span class="comment">// 系统时钟</span></span><br><span class="line">	<span class="keyword">input</span> 		 sys_rst_n,             <span class="comment">// 系统复位信号（低有效）</span></span><br><span class="line"> </span><br><span class="line">	<span class="keyword">output</span> [<span class="number">5</span>:<span class="number">0</span>] sel ,                  <span class="comment">// 数码管位选</span></span><br><span class="line">	<span class="keyword">output</span> [<span class="number">7</span>:<span class="number">0</span>] seg_led                <span class="comment">// 数码管段选</span></span><br><span class="line"> );</span><br><span class="line"> </span><br><span class="line"> <span class="comment">//parameter define</span></span><br><span class="line"> <span class="keyword">parameter</span> TIME_SHOW = <span class="number">25&#x27;d25000_000</span>;   <span class="comment">// 数码管变化的时间间隔0.5s</span></span><br><span class="line"> </span><br><span class="line"> <span class="comment">//wire define</span></span><br><span class="line"> <span class="keyword">wire</span> add_flag;                         <span class="comment">// 数码管变化的通知信号</span></span><br><span class="line">    </span><br><span class="line"> <span class="comment">//例化计时模块</span></span><br><span class="line">time_count #(                           <span class="comment">//参数例化使用’#‘</span></span><br><span class="line">	<span class="variable">.MAX_NUM</span> (TIME_SHOW)</span><br><span class="line">) u_time_count(</span><br><span class="line">	<span class="variable">.clk</span> (sys_clk ),</span><br><span class="line"> 	<span class="variable">.rst_n</span> (sys_rst_n),</span><br><span class="line"> 	<span class="variable">.flag</span> (add_flag )</span><br><span class="line"> );</span><br><span class="line"><span class="comment">//例化数码管静态显示模块</span></span><br><span class="line">seg_led_static u_seg_led_static (</span><br><span class="line">	<span class="variable">.clk</span> (sys_clk ),</span><br><span class="line"> 	<span class="variable">.rst_n</span> (sys_rst_n),</span><br><span class="line"> 	<span class="variable">.add_flag</span> (add_flag ),</span><br><span class="line"> 	<span class="variable">.sel</span> (sel ),</span><br><span class="line">	<span class="variable">.seg_led</span> (seg_led )</span><br><span class="line"> );</span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<p>​        上面给出了顶层模块的完整代码，子模块只有模块的端口和参数定义的代码。这是因为顶层模块对子模块做例化时，只需要知道子模块的端口信号名，而不用关心子模块内部具体是如何实现的。</p>
<p>​        如果子模块内部使用parameter 定义了一些参数，Verilog 也支持对参数的例化（也叫参数的传递），即顶层模块可以通过例化参数来修改子模块内定义的参数。<br>​        <strong>下图为模块例化</strong></p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261455692.png"></p>
<p>​        上图右侧是例化的数码管静态显示模块，子模块名是指被例化模块的模块名，而例化模块名相当于标识，当例化多个相同模块时，可以通过例化名来识别哪一个例化，我们一般命名为“u_”+“子模块名”。信号列表中“.”之后的信号是数码管静态显示模块定义的端口信号，括号内的信号则是顶层模块声明的信号，这样就将顶层模块的信号与子模块的信号一一对应起来，同时需要注意信号的位宽要保持一致。</p>

      
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          <p>​        原文地址：<a target="_blank" rel="noopener" href="https://www.bilibili.com/video/BV1SS4y1z7Zm/?p=14&amp;spm_id_from=pageDriver&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8">https://www.bilibili.com/video/BV1SS4y1z7Zm/?p=14&amp;spm_id_from=pageDriver&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8</a></p>
<h3 id="一、实验原理"><a href="#一、实验原理" class="headerlink" title="一、实验原理"></a>一、实验原理</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261107147.png" style="zoom:80%;">

<h3 id="二、代码"><a href="#二、代码" class="headerlink" title="二、代码"></a>二、代码</h3><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br><span class="line">71</span><br><span class="line">72</span><br><span class="line">73</span><br><span class="line">74</span><br><span class="line">75</span><br><span class="line">76</span><br><span class="line">77</span><br><span class="line">78</span><br><span class="line">79</span><br><span class="line">80</span><br><span class="line">81</span><br><span class="line">82</span><br><span class="line">83</span><br><span class="line">84</span><br><span class="line">85</span><br><span class="line">86</span><br><span class="line">87</span><br><span class="line">88</span><br><span class="line">89</span><br><span class="line">90</span><br><span class="line">91</span><br><span class="line">92</span><br><span class="line">93</span><br><span class="line">94</span><br><span class="line">95</span><br></pre></td><td class="code"><pre><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_idle      3&#x27;b001</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_led_on    3&#x27;b010</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_led_off   3&#x27;b100</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> fsm_ctrl3(</span><br><span class="line">    <span class="keyword">input</span>         fpga_clk,        <span class="comment">//FPGA PL clock, 50 MHz</span></span><br><span class="line">    <span class="keyword">input</span>         rst_n,           <span class="comment">//FPGA reset pin</span></span><br><span class="line">    <span class="keyword">output</span> [<span class="number">2</span>:<span class="number">0</span>]  fpga_led         <span class="comment">//[2:0]:表征该信号的位宽</span></span><br><span class="line">    );</span><br><span class="line">    </span><br><span class="line"><span class="comment">//time_cnt循环计数，周期约1秒(从0计数到50000000-1)   </span></span><br><span class="line"><span class="keyword">reg</span> [<span class="number">31</span>:<span class="number">0</span>]  time_cnt;      <span class="comment">//无符号的32位数</span></span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        time_cnt &lt;= <span class="number">32&#x27;d0</span>;</span><br><span class="line">    <span class="keyword">else</span> <span class="keyword">if</span>(time_cnt == <span class="number">32&#x27;d49000000</span>) </span><br><span class="line">        time_cnt &lt;= <span class="number">32&#x27;d0</span>;</span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        time_cnt &lt;= time_cnt + <span class="number">1&#x27;d1</span>;   </span><br><span class="line">    </span><br><span class="line"><span class="comment">//产生状态改变的输入信号 </span></span><br><span class="line"><span class="keyword">reg</span>   state_sig;</span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b0</span>;</span><br><span class="line">    <span class="keyword">else</span> <span class="keyword">if</span>(time_cnt == <span class="number">32&#x27;d49000000</span>)</span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b1</span>;</span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b0</span>; </span><br><span class="line">        </span><br><span class="line"><span class="comment">//定义两个常量 </span></span><br><span class="line"><span class="keyword">parameter</span> LED_OFF = <span class="number">3&#x27;b000</span>;</span><br><span class="line"><span class="keyword">parameter</span> LED_ON  = <span class="number">3&#x27;b100</span>;</span><br><span class="line">    </span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]   led_r;</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]   led_current_state;</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]   led_next_state;        </span><br><span class="line">        </span><br><span class="line"><span class="comment">//时序逻辑，控制状态跳转</span></span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        led_current_state &lt;= <span class="meta">`state_idle;</span></span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        led_current_state &lt;= led_next_state;</span><br><span class="line">        </span><br><span class="line"><span class="comment">//组合逻辑，控制状态跳转条件及状态输出</span></span><br><span class="line"><span class="keyword">always</span>@(led_current_state <span class="keyword">or</span> state_sig <span class="keyword">or</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        <span class="keyword">begin</span></span><br><span class="line">            led_next_state = <span class="meta">`state_idle;</span></span><br><span class="line">        <span class="keyword">end</span></span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        <span class="keyword">case</span>(led_current_state)</span><br><span class="line">            <span class="meta">`state_idle:begin</span></span><br><span class="line">                <span class="keyword">if</span>(state_sig)     <span class="comment">//触发信号有效，则跳转到led_on状态，否则，保持当前状态</span></span><br><span class="line">                    <span class="keyword">begin</span></span><br><span class="line">                        led_next_state = <span class="meta">`state_led_on;</span></span><br><span class="line">                    <span class="keyword">end</span></span><br><span class="line">                <span class="keyword">else</span></span><br><span class="line">                    led_next_state = <span class="meta">`state_idle;</span></span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">            <span class="meta">`state_led_on:begin</span></span><br><span class="line">                <span class="keyword">if</span>(state_sig)</span><br><span class="line">                    <span class="keyword">begin</span></span><br><span class="line">                        led_next_state = <span class="meta">`state_led_off;</span></span><br><span class="line">                    <span class="keyword">end</span></span><br><span class="line">                <span class="keyword">else</span></span><br><span class="line">                    led_next_state = <span class="meta">`state_led_on;</span></span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">            <span class="meta">`state_led_off:begin</span></span><br><span class="line">                <span class="keyword">if</span>(state_sig)</span><br><span class="line">                    <span class="keyword">begin</span></span><br><span class="line">                        led_next_state = <span class="meta">`state_led_on;</span></span><br><span class="line">                    <span class="keyword">end</span></span><br><span class="line">                <span class="keyword">else</span></span><br><span class="line">                    led_next_state = <span class="meta">`state_led_off;</span></span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">            <span class="keyword">default</span>:</span><br><span class="line">                led_next_state = <span class="meta">`state_idle;</span></span><br><span class="line">        <span class="keyword">endcase</span>   </span><br><span class="line">        </span><br><span class="line"><span class="comment">//逻辑输出</span></span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        led_r &lt;= LED_OFF;</span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        <span class="keyword">case</span>(led_next_state)</span><br><span class="line">            <span class="meta">`state_idle:     led_r &lt;= LED_ON;</span></span><br><span class="line">            <span class="meta">`state_led_on:   led_r &lt;= LED_ON;</span></span><br><span class="line">            <span class="meta">`state_led_off:  led_r &lt;= LED_OFF;</span></span><br><span class="line">        <span class="keyword">endcase</span></span><br><span class="line"> </span><br><span class="line"> <span class="comment">//led状态输出</span></span><br><span class="line"> <span class="keyword">assign</span> fpga_led = led_r;</span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
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          <p>​        原文地址：<a target="_blank" rel="noopener" href="https://www.bilibili.com/video/BV1SS4y1z7Zm?p=12&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8">https://www.bilibili.com/video/BV1SS4y1z7Zm?p=12&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8</a></p>
<h3 id="一、实验原理"><a href="#一、实验原理" class="headerlink" title="一、实验原理"></a>一、实验原理</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303212012038.png" style="zoom:80%;">

<h3 id="二、代码讲解"><a href="#二、代码讲解" class="headerlink" title="二、代码讲解"></a>二、代码讲解</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303212025073.png" style="zoom:80%;">

<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br></pre></td><td class="code"><pre><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_idle      3&#x27;d0</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_led_on    3&#x27;d1</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_led_off   3&#x27;d2</span></span><br><span class="line"></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> fsm_ctrl1(</span><br><span class="line">    <span class="keyword">input</span>         fpga_clk,        <span class="comment">//FPGA PL clock, 50 MHz</span></span><br><span class="line">    <span class="keyword">input</span>         rst_n,           <span class="comment">//FPGA reset pin</span></span><br><span class="line">    <span class="keyword">output</span> [<span class="number">2</span>:<span class="number">0</span>]  fpga_led         <span class="comment">//[2:0]:表征该信号的位宽</span></span><br><span class="line">    );</span><br><span class="line">    </span><br><span class="line">    </span><br><span class="line"><span class="comment">//time_cnt循环计数，周期约1秒(从0计数到50000000-1)   </span></span><br><span class="line"><span class="keyword">reg</span> [<span class="number">31</span>:<span class="number">0</span>]  time_cnt;      <span class="comment">//无符号的32位数</span></span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        time_cnt &lt;= <span class="number">32&#x27;d0</span>;</span><br><span class="line">    <span class="keyword">else</span> <span class="keyword">if</span>(time_cnt == <span class="number">32&#x27;d49000000</span>) </span><br><span class="line">        time_cnt &lt;= <span class="number">32&#x27;d0</span>;</span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        time_cnt &lt;= time_cnt + <span class="number">1&#x27;d1</span>;   </span><br><span class="line">    </span><br><span class="line">    </span><br><span class="line"><span class="keyword">reg</span>   state_sig;</span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b0</span>;</span><br><span class="line">    <span class="keyword">else</span> <span class="keyword">if</span>(time_cnt == <span class="number">32&#x27;d49000000</span>)</span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b1</span>;</span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b0</span>;</span><br><span class="line">        </span><br><span class="line"><span class="keyword">parameter</span> LED_OFF = <span class="number">3&#x27;b000</span>;</span><br><span class="line"><span class="keyword">parameter</span> LED_ON  = <span class="number">3&#x27;b100</span>;</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]  led;</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]  led_state;</span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        <span class="keyword">begin</span></span><br><span class="line">            led &lt;= <span class="number">3&#x27;b000</span>;            <span class="comment">//复位状态，3个led都灭      </span></span><br><span class="line">            led_state &lt;= <span class="meta">`state_idle;</span></span><br><span class="line">        <span class="keyword">end</span></span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        <span class="keyword">case</span>(led_state)</span><br><span class="line">            <span class="meta">`state_idle:begin</span></span><br><span class="line">                    led &lt;= <span class="number">3&#x27;b001</span>;       <span class="comment">//led3亮</span></span><br><span class="line">                    <span class="keyword">if</span>(state_sig)        <span class="comment">//检测到计时1秒标志信号，进入LED亮状态</span></span><br><span class="line">                        led_state &lt;= <span class="meta">`state_led_on;  //此时只是状态的转移，LED状态还未改变</span></span><br><span class="line">                    <span class="keyword">else</span></span><br><span class="line">                        led_state &lt;= led_state;</span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">            <span class="meta">`state_led_on:begin</span></span><br><span class="line">                    led &lt;= LED_ON;       <span class="comment">//进入LED亮状态后点亮led1</span></span><br><span class="line">                    <span class="keyword">if</span>(state_sig)</span><br><span class="line">                        led_state &lt;= <span class="meta">`state_led_off;</span></span><br><span class="line">                    <span class="keyword">else</span></span><br><span class="line">                        led_state &lt;= led_state;</span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">            <span class="meta">`state_led_off:begin</span></span><br><span class="line">                    led &lt;= LED_OFF;      <span class="comment">//关闭所有led</span></span><br><span class="line">                    <span class="keyword">if</span>(state_sig)</span><br><span class="line">                        led_state &lt;= <span class="meta">`state_led_on;</span></span><br><span class="line">                    <span class="keyword">else</span></span><br><span class="line">                        led_state &lt;= led_state;</span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">        <span class="keyword">endcase</span></span><br><span class="line">        </span><br><span class="line"><span class="keyword">assign</span> fpga_led = led;</span><br><span class="line"></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<p>​        管脚绑定的时候如下图所示：</p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303222104872.png"></p>
<p>​        最后的效果时这样的：正常情况下D3这个灯一秒一闪，如果按下K3按键，则D1亮然后再灭掉，然后D3一闪一闪。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303222107825.png" style="zoom:80%;">


      
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          <p>​        原文地址：<a target="_blank" rel="noopener" href="https://www.bilibili.com/video/BV1SS4y1z7Zm?p=13&amp;spm_id_from=pageDriver&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8">https://www.bilibili.com/video/BV1SS4y1z7Zm?p=13&amp;spm_id_from=pageDriver&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8</a></p>
<h3 id="一、实验原理"><a href="#一、实验原理" class="headerlink" title="一、实验原理"></a>一、实验原理</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303222144821.png" style="zoom:80%;">

<h3 id="二、代码讲解"><a href="#二、代码讲解" class="headerlink" title="二、代码讲解"></a>二、代码讲解</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303222145093.png" style="zoom:80%;">

<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br><span class="line">71</span><br><span class="line">72</span><br><span class="line">73</span><br><span class="line">74</span><br><span class="line">75</span><br><span class="line">76</span><br><span class="line">77</span><br><span class="line">78</span><br><span class="line">79</span><br><span class="line">80</span><br><span class="line">81</span><br><span class="line">82</span><br><span class="line">83</span><br><span class="line">84</span><br><span class="line">85</span><br><span class="line">86</span><br><span class="line">87</span><br><span class="line">88</span><br></pre></td><td class="code"><pre><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_idle      3&#x27;b001</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_led_on    3&#x27;b010</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">define</span> state_led_off   3&#x27;b100</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> fsm_ctrl2(</span><br><span class="line">    <span class="keyword">input</span>         fpga_clk,        <span class="comment">//FPGA PL clock, 50 MHz</span></span><br><span class="line">    <span class="keyword">input</span>         rst_n,           <span class="comment">//FPGA reset pin</span></span><br><span class="line">    <span class="keyword">output</span> [<span class="number">2</span>:<span class="number">0</span>]  fpga_led         <span class="comment">//[2:0]:表征该信号的位宽</span></span><br><span class="line">    );</span><br><span class="line">    </span><br><span class="line"><span class="comment">//time_cnt循环计数，周期约1秒(从0计数到50000000-1)   </span></span><br><span class="line"><span class="keyword">reg</span> [<span class="number">31</span>:<span class="number">0</span>]  time_cnt;      <span class="comment">//无符号的32位数</span></span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        time_cnt &lt;= <span class="number">32&#x27;d0</span>;</span><br><span class="line">    <span class="keyword">else</span> <span class="keyword">if</span>(time_cnt == <span class="number">32&#x27;d49000000</span>) </span><br><span class="line">        time_cnt &lt;= <span class="number">32&#x27;d0</span>;</span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        time_cnt &lt;= time_cnt + <span class="number">1&#x27;d1</span>;   </span><br><span class="line">    </span><br><span class="line"><span class="comment">//每计数满1秒，拉高一个脉冲信号</span></span><br><span class="line"><span class="keyword">reg</span>   state_sig;</span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b0</span>;</span><br><span class="line">    <span class="keyword">else</span> <span class="keyword">if</span>(time_cnt == <span class="number">32&#x27;d49000000</span>)</span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b1</span>;</span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        state_sig &lt;= <span class="number">1&#x27;b0</span>; </span><br><span class="line"> </span><br><span class="line"><span class="comment">//定义两个常量 </span></span><br><span class="line"><span class="keyword">parameter</span> LED_OFF = <span class="number">3&#x27;b000</span>;</span><br><span class="line"><span class="keyword">parameter</span> LED_ON  = <span class="number">3&#x27;b100</span>;</span><br><span class="line">    </span><br><span class="line"></span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]   led_r;</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]   led_current_state;</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">2</span>:<span class="number">0</span>]   led_next_state;</span><br><span class="line"></span><br><span class="line"><span class="comment">//时序逻辑，控制状态跳转</span></span><br><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> fpga_clk <span class="keyword">or</span> <span class="keyword">negedge</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        led_current_state &lt;= <span class="meta">`state_idle;</span></span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        led_current_state &lt;= led_next_state;</span><br><span class="line">        </span><br><span class="line"><span class="comment">//组合逻辑，控制状态跳转条件及状态输出</span></span><br><span class="line"><span class="keyword">always</span>@(led_current_state <span class="keyword">or</span> state_sig <span class="keyword">or</span> rst_n)</span><br><span class="line">    <span class="keyword">if</span>(!rst_n)</span><br><span class="line">        <span class="keyword">begin</span></span><br><span class="line">            led_r = LED_ON;</span><br><span class="line">            led_next_state = <span class="meta">`state_idle;</span></span><br><span class="line">        <span class="keyword">end</span></span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">        <span class="keyword">case</span>(led_current_state)</span><br><span class="line">            <span class="meta">`state_idle:begin</span></span><br><span class="line">                <span class="keyword">if</span>(state_sig)           <span class="comment">//触发信号有效，则跳转到led_on状态，否则，保持当前状态</span></span><br><span class="line">                    <span class="keyword">begin</span></span><br><span class="line">                        led_next_state = <span class="meta">`state_led_on;</span></span><br><span class="line">                    <span class="keyword">end</span></span><br><span class="line">                <span class="keyword">else</span></span><br><span class="line">                    led_next_state = <span class="meta">`state_idle;</span></span><br><span class="line">                    led_r = LED_OFF;               <span class="comment">//熄灭LED</span></span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">            <span class="meta">`state_led_on:begin</span></span><br><span class="line">                <span class="keyword">if</span>(state_sig)</span><br><span class="line">                    <span class="keyword">begin</span></span><br><span class="line">                        led_next_state = <span class="meta">`state_led_off;</span></span><br><span class="line">                    <span class="keyword">end</span></span><br><span class="line">                <span class="keyword">else</span></span><br><span class="line">                    led_next_state = <span class="meta">`state_led_on;</span></span><br><span class="line">                    led_r = LED_ON;                <span class="comment">//点亮LED</span></span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">            <span class="meta">`state_led_off:begin</span></span><br><span class="line">                <span class="keyword">if</span>(state_sig)</span><br><span class="line">                    <span class="keyword">begin</span></span><br><span class="line">                        led_next_state = <span class="meta">`state_led_on;</span></span><br><span class="line">                    <span class="keyword">end</span></span><br><span class="line">                <span class="keyword">else</span></span><br><span class="line">                    led_next_state = <span class="meta">`state_led_off;</span></span><br><span class="line">                    led_r = LED_OFF;              <span class="comment">//熄灭LED</span></span><br><span class="line">                <span class="keyword">end</span></span><br><span class="line">        <span class="keyword">endcase</span>   </span><br><span class="line"></span><br><span class="line"></span><br><span class="line"><span class="comment">//控制led输出 </span></span><br><span class="line"><span class="keyword">assign</span> fpga_led = led_r;</span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<h3 id="三、波形仿真"><a href="#三、波形仿真" class="headerlink" title="三、波形仿真"></a>三、波形仿真</h3><p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303260955646.png"></p>
<p>​        为了方便看波形的仿真，这里将time_cnt加到最大25的时候就清0。</p>
<p>​        我们先看time_cnt，当加到25的时候，下一个时钟上升沿来的时候，time_cnt就会归0；同时把触发信号state_sig拉高一个时钟周期。</p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303260958707.png"></p>
<p>再看组合逻辑里面的敏感列表，分别有led_current_state，state_sig，rst_n。所以当state_sig置1的时候，led_next_state就直接发生跳转(<strong>state_sig和led_next_state同时变化的</strong>)。<strong>led_current_state状态会比led_next_state晚一个时钟周期。</strong></p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303261019296.png"></p>

      
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          <p>​    原文地址：<a target="_blank" rel="noopener" href="https://zhuanlan.zhihu.com/p/110543798">https://zhuanlan.zhihu.com/p/110543798</a></p>
<h3 id="时序逻辑和组合逻辑的区别"><a href="#时序逻辑和组合逻辑的区别" class="headerlink" title="时序逻辑和组合逻辑的区别"></a>时序逻辑和组合逻辑的区别</h3><p>​        关于组合逻辑和时序逻辑的不同，我们可以从三方面来理解，分别是code（代码），电路图和波形图三方面。</p>
<p>​        从代码层面来看，时序逻辑即敏感列表里面带有时钟上升沿，如果是没有上升沿或者是带有“*”号的代码，为组合逻辑。</p>
<p>​        电路层面，两种逻辑反映的电路也有不同，时序逻辑相当于在组合逻辑的基础上多了一个D触发器。</p>
<p>​        波形图层面，组合逻辑的波形是即刻反映变化的，与时钟无关；但是时序逻辑的波形不会立刻反映出来，只有在时钟的上升沿发生变化。</p>
<h3 id="简单例子"><a href="#简单例子" class="headerlink" title="简单例子"></a>简单例子</h3><p>​        用一个简单的例子来区分学习下，如计算c=a+b。</p>
<p>​        <strong>(1)在代码层面</strong>，时序逻辑代码表示如下，可以看到此代码有“posedge“时钟上升沿，即表示有一个D触发器，a+b的结果c是在D触发器发出指令后才进行输出的。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316150228.png" style="zoom:80%;">

<p>​        组合逻辑则如下所示，是不带上升沿的，有“*”号的，直接输出a+b=c的值，不进行额外操作：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316150324.png" style="zoom:80%;">

<p>​        对比两种逻辑的代码表示，可以看出同样是输出c的值，不同的逻辑输出时间却不同，时序逻辑是在时钟上升沿输出，组合逻辑则直接输出。</p>
<p>​        <strong>(2)电路图层面</strong>，组合逻辑为一个加法器连接a和b，紧接着立刻给到c，如下图所示，可以看到a+b得出的值c直接输出，没有进行任何额外操作：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316150535.png" style="zoom:80%;">

<p>​        时序逻辑的电路图加法器连接的a和b没有变，但是c的值在输出部分，不会直接输出，D触发器就像一扇门，信号值c‘停留在门前，当D触发器收到了时钟clk上升沿的信号，才会把门打开，输出信号c的值，如下图所示：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316150623.png" style="zoom:80%;">

<p>​        可以看到，组合逻辑是直接输出信号c，时序逻辑需要D触发器收到时钟上升沿信号后才会输出信号c。</p>
<p>​        <strong>(3)在波形图层面</strong>，我们可以画出时序图来分析，如下图所示。可以看出第一个时钟时a=1，b=2，此时组合逻辑立刻得出c=3，是跟时钟没有关系的；但是时序逻辑一定要在下一个时钟的上升沿处才得出c=3的结果；</p>
<p>​        以此类推，后面的原理是一样的，当a=2，b=4时，组合逻辑马上得出c=6，时序逻辑在第3个时钟上升沿得出c=6。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316150735.png" style="zoom:80%;">

<p>​        综上所述，我们进行一下总结，组合逻辑任意时刻的输出仅仅取决该时刻的输入，与时钟无关；时序逻辑先算好当前输入信号的结果，但还不影响输出，只有等到时钟上升沿的一瞬间，才把结果给了输出。</p>
<h3 id="时序逻辑和组合逻辑的使用"><a href="#时序逻辑和组合逻辑的使用" class="headerlink" title="时序逻辑和组合逻辑的使用"></a>时序逻辑和组合逻辑的使用</h3><p>​        首先我们需要保证信号的结果是正确的，只要满足目标需求，这时使用时序逻辑还是组合逻辑都是可以的（这里我们讨论的是大多数情况，但也有例外，例如模块的输出一般要求是时序逻辑）。</p>
<p>​        在实际设计中，为了便于操作，我们可以首先考虑用时序逻辑，看是否能满足设计要求。如果无法满足目标要求，需要凑时序，那么就考虑改为组合逻辑。</p>
<p>​        举个例子便于大家更好地理解，如下图所示，假设有一个模块，有两个信号dout和dout_vld，其中dout表示数据，dout_vld表示数据有效性。我们假设需要该模块先后输出两个数据6和1。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316150901.png" style="zoom:80%;">

<p>​        如下图所示，该波形输出就是正确的，只要设计能保证正确性，那不管使用组合逻辑还是时序逻辑，都是可以的。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316150945.png" style="zoom:80%;">

<p>​        但假设现在输出的结果如下图所示，输出的是8和5，不是我们目标需要的6和1，并且可以看到，dout_vld比dout晚了一个时钟，这个时候就可以考虑设计dout_vld的时序逻辑改为组合逻辑，将信号dout_vld提前一拍，就可以得到正确的结果。</p>
<p>​        另一种方法，假设dout是组合逻辑设计的，就是把dout改为时序逻辑实现，将dout推迟一拍，达到信号对齐的效果。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230316151035.png" style="zoom:80%;">

      
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          <p>​        原文来源：<a target="_blank" rel="noopener" href="https://www.bilibili.com/video/BV1h8411E7yi/?spm_id_from=333.999.0.0&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8">https://www.bilibili.com/video/BV1h8411E7yi/?spm_id_from=333.999.0.0&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8</a></p>
<h3 id="1-AXI4介绍"><a href="#1-AXI4介绍" class="headerlink" title="1.AXI4介绍"></a>1.AXI4介绍</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312093624.png" style="zoom:80%;">

<h4 id="1-1-什么是突发"><a href="#1-1-什么是突发" class="headerlink" title="1.1.什么是突发"></a>1.1.什么是突发</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312093900.png" style="zoom:80%;">

<h4 id="1-2-AXI-LITE通道介绍"><a href="#1-2-AXI-LITE通道介绍" class="headerlink" title="1.2.AXI_LITE通道介绍"></a>1.2.AXI_LITE通道介绍</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312094026.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312094140.png" style="zoom:80%;">

<h3 id="2-握手是什么"><a href="#2-握手是什么" class="headerlink" title="2.握手是什么"></a>2.握手是什么</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312094358.png" style="zoom:80%;">

<h4 id="2-1-主机如何将“写数据”写入到从机"><a href="#2-1-主机如何将“写数据”写入到从机" class="headerlink" title="2.1 主机如何将“写数据”写入到从机"></a>2.1 主机如何将“写数据”写入到从机</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312094734.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312094846.png" style="zoom:80%;">

<p>以WVALID和WREADY到达先后关系分为三类：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312095533.png" style="zoom:80%;">

<p>​        首先可以看到在T0的时刻，WVALID信号拉高了，说明主机开始发起了一个请求。然后再看T1时刻，检查到WREADY信号也为高，那就说明从机准备好了，写数据D0就成功写入到从机里了。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312095801.png" style="zoom:80%;">

<p>​        第二种情况，从机没有准备好怎么办？我们可以看到，T0时刻主机发起了请求，在T1时刻WREADY为低，说明从机没有准备好，那主机WVALID就一直保持。直到T3时刻，发现WREADY信号为高了，主机才将D0写入从机。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312100033.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312100158.png" style="zoom:80%;">

<h3 id="3-AXI-LITE端口信号及其功能"><a href="#3-AXI-LITE端口信号及其功能" class="headerlink" title="3.AXI_LITE端口信号及其功能"></a>3.AXI_LITE端口信号及其功能</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312100642.png" style="zoom:80%;">

<p>​        别看里面好像很多很乱不好记，其实很多都是类似的，比如你看<strong>写地址通道和读地址通道</strong>，他们基本是一样的，他们的功能也基本一样。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312101900.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312102836.png" style="zoom:80%;">

<h3 id="4-写和读过程"><a href="#4-写和读过程" class="headerlink" title="4.写和读过程"></a>4.写和读过程</h3><h4 id="4-1-写过程"><a href="#4-1-写过程" class="headerlink" title="4.1 写过程"></a>4.1 写过程</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312103043.png" style="zoom:80%;">

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<h4 id="4-2-读过程"><a href="#4-2-读过程" class="headerlink" title="4.2 读过程"></a>4.2 读过程</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230312103414.png" style="zoom:80%;">

      
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          <p>​        原文地址：<a target="_blank" rel="noopener" href="https://blog.csdn.net/Reborn_Lee/article/details/107052261">https://blog.csdn.net/Reborn_Lee/article/details/107052261</a></p>
<h3 id="语法"><a href="#语法" class="headerlink" title="语法"></a>语法</h3><p>​        语法很简单，如果按照结构划分可以分为：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span> @ (<span class="keyword">event</span>)</span><br><span class="line">	[statement]</span><br><span class="line"></span><br><span class="line"><span class="keyword">always</span> @ (<span class="keyword">event</span>) <span class="keyword">begin</span></span><br><span class="line">	[multiple statements]</span><br><span class="line"><span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p>​        第一种是块内只有一条语句，不需要使用begin end；第二种是有多条语法，需要使用begin end包裹起来。<br>这其实都是废话。我们推荐全部都用begin end包裹起来，这样形式比较固定，比较方面阅读以及形成固定风格。</p>
<p>​        我们按照下面方式划分，<strong>时序逻辑和组合逻辑区别划分</strong>,划分组合逻辑以及时序逻辑的依据是敏感列表里面的内容有没有边沿事件。</p>
<p>​        <strong>组合逻辑语法：</strong></p>
<p>括号内部的敏感列表仅仅为电平事件，例如：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(a,b,c,d) <span class="keyword">begin</span></span><br><span class="line">	out = a&amp;b&amp;c&amp;d;</span><br><span class="line"><span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p>​        这样写的缺点在于有的时候，敏感列表过多，一个一个加入太麻烦，容易忘掉，为了解决这个问题，verilog 2001标准说可以使用*替换敏感列表，表示缺省，编译器会根据always块内部的内容自动识别敏感变量。<br>如：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(*) <span class="keyword">begin</span></span><br><span class="line">	out = a&amp;b&amp;c&amp;d;</span><br><span class="line"><span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p>​        <strong>时序逻辑语法：</strong></p>
<p>​        时序逻辑的always块将内部敏感列表包括了边沿事件，一般是时钟边沿。例如我们描述一个同步复位的D触发器，可以这样描述：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> i_clk) <span class="keyword">begin</span></span><br><span class="line">	<span class="keyword">if</span>(i_rst) <span class="keyword">begin</span></span><br><span class="line">		q &lt;= <span class="number">0</span>;</span><br><span class="line">	<span class="keyword">end</span></span><br><span class="line">	<span class="keyword">else</span> <span class="keyword">begin</span></span><br><span class="line">		q &lt;= d;</span><br><span class="line">	<span class="keyword">end</span></span><br><span class="line"><span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p>​        这表示当检测到时钟上升沿时，判断是否复位有效，如果有效对输出复位，否则采样输入d值。</p>
<p>​        当然时序逻辑敏感列表中的边沿事件不一定只是时钟，也可以是其他边沿，例如描述一个异步复位的D触发器：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> i_clk <span class="keyword">or</span> <span class="keyword">negedge</span> i_rst) <span class="keyword">begin</span></span><br><span class="line">	<span class="keyword">if</span>(i_rst) <span class="keyword">begin</span></span><br><span class="line">		q &lt;= <span class="number">0</span>;</span><br><span class="line">	<span class="keyword">end</span></span><br><span class="line">	<span class="keyword">else</span> <span class="keyword">begin</span></span><br><span class="line">		q &lt;= d;</span><br><span class="line">	<span class="keyword">end</span></span><br><span class="line"><span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p>​        这表示当检测到时钟上升沿或者复位的上升沿时，都会触发always块内部的语句。<br>​        但是明显看出，复位的优先级更高，也就是说，当检测到复位的上升沿时，无论时钟边沿是否检测到都执行复位操作，否则，当检测到时钟上升沿时，采样输入值d。</p>
<h3 id="什么是敏感列表？"><a href="#什么是敏感列表？" class="headerlink" title="什么是敏感列表？"></a>什么是敏感列表？</h3><p>​        敏感列表就是触发always块内部语句的条件。</p>
<p>​        在下面的代码中，每当信号a或b的值发生变化时，always块中的所有语句都会被执行。</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// Execute always block whenever value of &quot;a&quot; or &quot;b&quot; change</span></span><br><span class="line"><span class="keyword">always</span> @ (a <span class="keyword">or</span> b) <span class="keyword">begin</span></span><br><span class="line">	[statements]</span><br><span class="line"><span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<h3 id="always块是用来干什么的？"><a href="#always块是用来干什么的？" class="headerlink" title="always块是用来干什么的？"></a>always块是用来干什么的？</h3><p>​        always块是Verilog中用来描述组合逻辑以及时序逻辑的语法。<br>​        需要补充的是一个设计中可以有多个always块，或者说一定有很多个always块。<br>​        这些硬件块都是相互独立同时工作的。每个块之间的连接是决定数据流的原因。为了模拟这种行为，<strong>一个always块被做成一个连续的过程（硬件不可能断断续续工作）</strong>，当敏感列表中的一个信号变化时，它就会被触发并执行一些动作（always块内的语句）。</p>
<h3 id="如果没有敏感列表怎么办？"><a href="#如果没有敏感列表怎么办？" class="headerlink" title="如果没有敏感列表怎么办？"></a>如果没有敏感列表怎么办？</h3><p>​        这个话题比较有意思，你可能说怎么可能没有敏感列表？其实，还真的可以没有敏感列表，这是仿真中的用法。我们经常使用没有敏感列表的always来表示不断的触发，用此特性来生成时钟。<br>​        例如：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span> #<span class="number">10</span> clk = ~clk;</span><br></pre></td></tr></table></figure>
<p>​        其实，always块内的敏感列表就是为了控制内部语句什么时候触发的。那么可以理解为一种定时，如果没有了敏感列表，则为零延迟，那么就会不断的触发，如下：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// always block is started at time 0 units</span></span><br><span class="line"><span class="comment">// But when is it supposed to be repeated ?</span></span><br><span class="line"><span class="comment">// There is no time control, and hence it will stay and</span></span><br><span class="line"><span class="comment">// be repeated at 0 time units only. This continues</span></span><br><span class="line"><span class="comment">// in a loop and simulation will hang !</span></span><br><span class="line"><span class="keyword">always</span> clk = ~clk;</span><br></pre></td></tr></table></figure>
<p>​        上面显示的示例是一个always块，它试图反转信号clk的值。该语句每0个时间单位执行一次。因此，由于语句中没有延迟，因此它将永远执行。</p>
<p>​        这是没有意义的，我们正确的做法应该给一个定时或延迟：</p>
<p>​        即使敏感度列表为空，也应该有其他形式的时间延迟。always如下所示，通过构造中的延迟语句来提前仿真时间。现在，每10个时间单位完成一次时钟反转。</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span> #<span class="number">10</span> clk = ~clk;</span><br></pre></td></tr></table></figure>
<p>​        当然，这种<strong>没有敏感列表的显示延迟，是不能综合的，只能用于仿真</strong>。</p>
<h3 id="注意事项"><a href="#注意事项" class="headerlink" title="注意事项"></a>注意事项</h3><p>​        always块内被赋值的变量（左值）都应该为reg类型。</p>

      
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          <p>​        原文来源：<a target="_blank" rel="noopener" href="https://www.bilibili.com/video/BV1FD4y1E79q/?spm_id_from=333.999.0.0&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8">https://www.bilibili.com/video/BV1FD4y1E79q/?spm_id_from=333.999.0.0&amp;vd_source=2ef3411e1c045a25cc2351abaa2c3ce8</a></p>
<h3 id="一、什么是AXI-GP-AXI-HP和AXI-ACP接口"><a href="#一、什么是AXI-GP-AXI-HP和AXI-ACP接口" class="headerlink" title="一、什么是AXI_GP,AXI_HP和AXI_ACP接口"></a>一、什么是AXI_GP,AXI_HP和AXI_ACP接口</h3><p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_20230305195113.png"></p>
<p>​        由上图可知，ARM和FPGA交互有三种接口，分别是GP,HP,ACP，这三个接口都是PS端的接口。为什么要弄三个接口呢？因为PS发送数据的时候，有的时候发送的比较快，有的时候发送的比较慢。</p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_20230305195912.png"></p>
<p>HP和ACP之间的区别后面再讲，其实这三个接口不用去强记。我们打开Vivado，点击左边的“Create Block Design”</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062210393.png" style="zoom:67%;">

<p>点击加号，Add IP</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062212325.png" style="zoom:67%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062214637.png" style="zoom:67%;">

<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062215308.png"></p>
<p>这里可以看到有三个接口，一个是AXI GP接口，一个是AXI HP接口，以及右边的AXI ACP接口。</p>
<h3 id="二、AXI4"><a href="#二、AXI4" class="headerlink" title="二、AXI4"></a>二、AXI4</h3><h4 id="2-1-AXI4介绍"><a href="#2-1-AXI4介绍" class="headerlink" title="2.1 AXI4介绍"></a>2.1 AXI4介绍</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062222072.png" style="zoom:80%;">

<h4 id="2-2-什么是片内，片外"><a href="#2-2-什么是片内，片外" class="headerlink" title="2.2 什么是片内，片外"></a>2.2 什么是片内，片外</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062225587.png" style="zoom:80%;">

<h4 id="2-3-主与从的理解"><a href="#2-3-主与从的理解" class="headerlink" title="2.3 主与从的理解"></a>2.3 主与从的理解</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062227008.png" style="zoom:80%;">

<h3 id="三、AXI-GP-AXI-HP和AXI-ACP接口的主与从"><a href="#三、AXI-GP-AXI-HP和AXI-ACP接口的主与从" class="headerlink" title="三、AXI_GP,AXI_HP和AXI_ACP接口的主与从"></a>三、AXI_GP,AXI_HP和AXI_ACP接口的主与从</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062232519.png" style="zoom:80%;">

<p>这个表格不用强记，zynq那个block中可以知道的。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062237325.png" style="zoom:80%;">

<h3 id="四、常用的接口介绍"><a href="#四、常用的接口介绍" class="headerlink" title="四、常用的接口介绍"></a>四、常用的接口介绍</h3><h4 id="4-1-采用AXI-HP接口，PL为主机，PS为从机"><a href="#4-1-采用AXI-HP接口，PL为主机，PS为从机" class="headerlink" title="4.1 采用AXI_HP接口，PL为主机，PS为从机"></a>4.1 采用AXI_HP接口，PL为主机，PS为从机</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062244837.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062245366.png" style="zoom:80%;">

<p>上面这个是简图，也可以看下面这个zynq的这个图，类似的。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062252308.png" style="zoom:80%;">

<p>​        PS也可以向DDR3写入或者读取数据，DDR3相对于PS而言就是一个外设。</p>
<p>​        PS首先将数据写入到Cache，Cache里面的数据再写入到DDR3 contorller,最后到DDR3，反过来，PS也可以从DDR3里面读取数据。</p>
<p>​        PL将数据通过AXI_HP接口写入到DDR3, PS再将数据从DDR3里面读出来，这样就实现了PL和PS的数据交互。</p>
<h4 id="4-2-采用AXI-GP接口，PL为从机，PS为主机"><a href="#4-2-采用AXI-GP接口，PL为从机，PS为主机" class="headerlink" title="4.2 采用AXI_GP接口，PL为从机，PS为主机"></a>4.2 采用AXI_GP接口，PL为从机，PS为主机</h4><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062257893.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062300055.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062304091.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062307688.png" style="zoom:80%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062311851.png" style="zoom:80%;">

<h3 id="五、AXI-HP-AXI-GP-AXI-ACP理论带宽"><a href="#五、AXI-HP-AXI-GP-AXI-ACP理论带宽" class="headerlink" title="五、AXI_HP,AXI_GP,AXI_ACP理论带宽"></a>五、AXI_HP,AXI_GP,AXI_ACP理论带宽</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062317459.png" style="zoom:80%;">

<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202303062320504.png"></p>

      
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          <p>​        在杰理AC6956C的VM区域保存了一些参数，然后后面项目中程序有更新，需要重新烧录，但是不希望把VM区域的参数也擦除，折腾了很久，终于可以了，中间咨询了代理商和原厂。</p>
<p>​        默认sdk里面VM区域占用的位置是根据代码量会自动变化的，VM跟随在代码后面。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230221193647.png" style="zoom:67%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20230221193807.png" style="zoom:67%;">

<p>​            原厂说可以手动设置VM的地址，后来手动设置了VM地址，确实实现了要的功能。</p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_20230221193935.png"></p>
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